Pin outputs study data and status alerts

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When SK is large stage and CS is modified from large degree to low stage, AK6420A/40A/80A can receive theinstructions. CS ought to be retained reduced level although obtaining op-code, handle and data and when outputting info.

If CS is changed to high stage in the course of the above period, AK6420A/40A/80A stops the instruction execution.When SK is minimal and CS is modified from higher amount to lower amount, AK6420A/40A/80A might be in standing outputmode.

The CS need not be very low stage throughout the automated create time-out time period (Hectic status).SK (Serial Clock)The SK clock pin would be the synchronous clock enter for input/output knowledge.

At compose procedure, AK6420A/40A/80Atakes in the produce information from data enter pin (DI) synchronously with soaring fringe of input pulse of serial clock pin(SK).

And at study operation, AK6420A/40A/80A requires out the read through details to knowledge output pin (DO)synchronously with slipping fringe of SK.

The SK clock is just not necessary all through the automated write time-out period of time(Chaotic standing), the standing output period of time and in the event the product is just not selected (CS = significant amount).DI (Facts Enter)The op-code, handle and compose facts is input towards the DI pin.

DO (Details Output)The DO pin outputs the go through facts and status sign and will be higher impedance apart from this timing.RDY/BUSY (Ready/Busy position)This pin outputs the interior programming standing.

When the AK6420A/40A/80A is in the automated publish time-out period of time, this pin outputs the reduced amount (Occupied position), and outputs the high amount except for this timing.

The SDA pin is generally pulled superior having an exterior device

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Knowledge adjustments during SCL substantial intervals will show a start or halt issue as outlined under. Start Affliction: A high-to-low transition of SDA with SCL significant is a commence situation which should precede almost every other command.

Quit Issue: A low-to-high changeover of SDA with SCL high is usually a quit issue which ter- minates all communications. Right after a browse sequence, the end command will location the EEPROM inside a standby energy mode.

Admit: All addresses and information text are serially transmitted to and through the EEPROM in 8-bit text. Any machine to the system bus getting information (when communicating along with the EEPROM) will have to pull the SDA bus lower to accept that it's effectively gained every single word.

This ought to happen all through the ninth clock cycle after every single word gained and in spite of everything other process equipment have freed the SDA bus. The EEPROM will similarly acknowledge by pull- ing SDA very low soon after obtaining every single deal with or facts phrase.

STANDBY Mode: The AT24C11 options a reduced power standby method which happens to be enabled: (a) upon power-up and (b) following the receipt of the Stop bit as well as the completion of any inside functions.

Device Operation CLOCK and DATA TRANSITIONS

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The SDA pin is normally pulled high with an exter-nal device. Data on the SDA pin may change only during SCL low time periods.

Data changes during SCL high periods will indicate a start or stop condition asdefined below.Data ValiditySTART CONDITION: A high-to-low transition of SDA with SCL high is a start conditionthat must precede any other command.

Start and Stop DefinitionSTOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.After a read sequence, the stop command will place the EEPROM in a standby powermode .ACKNOWLEDGE: All addresses and data words are serially transmitted to and fromthe EEPROM in 8-bit words.

The EEPROM sends a “0” to acknowledge that it hasreceived each word. This happens during the ninth clock cycle.STANDBY MODE: The AT24C02A/04A/08A/16A features a low-power standby modethat is enabled: (a) upon power-up and (b) after the receipt of the Stop bit and the com-pletion of any internal operations.

After an interruption in protocol, power loss or system reset, anytwo-wire part can be reset by following these steps: 1. Clock up to 9 cycles2. Look for SDA high in each cycle while SCL is high3. Create a start condition as SDA is high.